List of Messages
Parent topic: List of Messages

ID:186070 Transmitter fast PLL "<name>" has clock output with differential I/O standard <name> and frequency of <name>, which is more than <name> limit

CAUSE: You specified a transmitter fast PLL with the specified clock output frequency and the specified differential I/O I/O standard. However, the clock output frequency exceeds the specified limit.

ACTION: Modify the design so that the clock output frequency for the fast PLL is within the required limit.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.