List of Messages |
CAUSE: The specified gigabit transceiver block (GXB) transmitter channel requires a user-reset sequence through the txdigitalreset port of its associated XGMII state machine. The tx_coreclk (phase compensation FIFO write clock) is not sourced by the coreclk_out port of its associated gigabit transceiver block (GXB) transmitter PLL. A user-reset sequence is required to ensure that the read and write pointers of the GXB transmitter channel's phase compensation FIFO are correctly initialized.
ACTION: Modify the design to drive the txdigitalreset port of the XGMII state machine associated with the GXB transmitter channel.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.