ID:186127 GXB transmitter channel "<name>" requires that a digitalreset signal be connected through its associated XGMII state machine and not be GND. The tx_coreclk port of the GXB transmitter channel is sourced by node "<name>" and not by the coreclk_out port of its associated GXB transmitter PLL

CAUSE: The specified gigabit transceiver block (GXB) transmitter channel requires a user-reset sequence through the txdigitalreset port of its associated XGMII state machine. The tx_coreclk (phase compensation FIFO write clock) is not sourced by the coreclk_out port of its associated gigabit transceiver block (GXB) transmitter PLL. A user-reset sequence is required to ensure that the read and write pointers of the GXB transmitter channel's phase compensation FIFO are correctly initialized.

ACTION: Modify the design to drive the txdigitalreset port of the XGMII state machine associated with the GXB transmitter channel.