ID:186126 GXB receiver channel "<name>" requires that an rxdigitalreset signal be connected through its associated XGMII state machine and not be GND. The rx_coreclk port of the GXB receiver channel is sourced by node "<name>" and not by the coreclk_out port of its associated GXB transmitter PLL

CAUSE: The specified gigabit transceiver block (GXB) receiver channel requires a user-reset sequence through the rxdigitalreset port of its associated XGMII state machine. The rx_coreclk (phase compensation FIFO read clock) is not sourced by the coreclk_out port of its associated gigabit transceiver block (GXB) transmitter PLL. A user-reset sequence is required to ensure that the read and write pointers of the GXB receiver channel's phase compensation FIFO are correctly initialized.

ACTION: Modify the design to drive the rxdigitalreset port of the XGMII state machine associated with the GXB receiver channel.