List of Messages |
CAUSE: The specified gigabit transceiver block (GXB) receiver channel requires a user-reset sequence through the rxdigitalreset port of its associated XGMII state machine. The rx_coreclk (phase compensation FIFO read clock) is not sourced by its rx_clkout port. A user-reset sequence is required to ensure that the read and write pointers of the GXB receiver channel's phase compensation FIFO are correctly initialized.
ACTION: Modify the design to drive the rxdigitalreset port of the XGMII state machine associated with the GXB receiver channel.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.