ID:186119 coreclk input ports (phase compensation FIFO read clock) of the following GXB receiver channels (which are in double data width mode) are sourced by the following signals. There is a possibility that bytes may be reordered at the receive parallel interface (GXB receiver channel data outputs) from the GXB. Contact Altera Applications for further information

CAUSE: The coreclk input ports of the specified gigabit transceiver block (GXB) receiver channels (which are in double data width mode), are sourced by specified signals other than the coreclk_out output signal of the gigabit transceiver block (GXB) transmitter PLL associated with this GXB receiver channel. There is a possibility that bytes may be reordered at the receive parallel interface (GXB receiver channel data outputs) from the GXB. The submessage(s) of this message list the GXB receiver channels and the signals that source them.

ACTION: Contact Altera Applications for further information.