List of Messages |
CAUSE: The coreclk input ports of the specified gigabit transceiver block (GXB) receiver channels (which are in double data width mode), are sourced by the specified signals other than the GXB receiver clock output signal. There is a possibility that bytes may be reordered at the receive parallel interface (GXB receiver channel data outputs) from the GXB. The submessage(s) of this message list the GXB receiver channels and the signals that source them.
ACTION: Contact Altera Applications for further information.
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