ID:186278 Switched primary clock for PLL "<name>" to inclk0 and connected its primary input clock pin "<name>" to inclk0 input port of the PLL because <name> is assigned to an I/O pin that feeds inclk0, not inclk1, input port of the PLL

CAUSE: You assigned the specified clock input pin, inclk1, as the primary clock of the specified PLL, and you assigned the specified input clock to an I/O pin. However, the I/O pin can feed only the clock input port inclk0 of the specified PLL, which is not the primary clock input port you selected. Therefore, the Fitter switched the primary clock for the specified PLL and connected the primary clock input pin to input port inclk0 of the PLL.

ACTION: Delete or change the location assignment for the specified clock input pin, or modify the design to change the primary clock for the PLL to inclk0.