List of Messages |
CAUSE: You assigned the specified clock input pin, inclk0, as the primary clock of the specified PLL, and you assigned the specified input clock to an I/O pin. However, the I/O pin can feed only the clock input port inclk1 of the specified PLL, which is not the primary clock input port you selected. Therefore, the Fitter switched the primary clock for the specified PLL and connected the primary clock input pin to input port inclk1 of the PLL.
ACTION: Delete or change the location assignment for the specified clock input pin, or modify the design to change the primary clock for the PLL to inclk1.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.