ID:186281 Output pin "<name>", external output clock of PLL "<name>", uses I/O standard <name> and has output clock frequency of <name>, but target device can support only maximum output clock frequency of <name> for I/O standard

CAUSE: You specified the output clock frequency and the specified I/O standard for the specified output pin, which is an external output clock of the specified PLL. However, the output clock frequency is higher than the maximum output clock frequency the target device can support for the I/O standard.

ACTION: Modify the design so that the output frequency of the PLL is less than the maximum frequency.