| List of Messages | |
CAUSE: You attempted to optimize netlists during synthesis by directing the Quartus Prime software to perform gate-level register retiming, specified a formal verification tool for the current project, and compiled the design. However, formal verification may give mismatches between the pre- and post-Quartus Prime netlists if the logic feeding registers is modified in the design due to this option.
ACTION: Specify that the Quartus Prime software not perform gate-level register retiming, and recompile the design.
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