List of Messages |
CAUSE: The specified RAM in your design uses an external clock signal directly from a pin. If the clock signal does not meet the minimum pulse width specifications (clock high time and clock low time) at all times when performing a write operation, new data may not be written correctly to the memory block, and may result in unexpected memory behavior.
ACTION: Use the on-chip phase-locked loop (PLL) as the input clock source to the memory block.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.