ID:185021 Detected external clock signal directly connected to the RAM "<name>" <name> port. This connection may cause unexpected memory behavior if your external clock signal violates the minimum pulse width specifications (clock high time and clock low time).

CAUSE: The specified RAM in your design uses an external clock signal directly from a pin. If the clock signal does not meet the minimum pulse width specifications (clock high time and clock low time) at all times when performing a write operation, new data may not be written correctly to the memory block, and may result in unexpected memory behavior.

ACTION: Use the on-chip phase-locked loop (PLL) as the input clock source to the memory block.