List of Messages |
CAUSE: The input clock of the specified PLL is not driven by a dedicated input pin. As a result, the input clock may have reduced jitter performance. Jitter performance depends on the switching rate of other design elements. This can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.
ACTION: If you want the specified input clock have better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL.
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