List of Messages |
CAUSE: You assigned two Input Delay from Pin to Internal Cells delay chain logic options to the combinational output port on specified I/O cell and assigned the Fast Input Register logic option to either the I/O cell or one of the logic cells fed by the I/O cell. An I/O cell that uses both delay chain settings cannot be packed with a register.
ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, remove either the Fast Input Register logic option or the delay chain logic options from the I/O cell.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.