List of Messages |
CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However, the Fitter cannot pack the nodes because the node to be packed is in QFBK mode.
ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, make sure that there is not a Fast Output Register, and/or Fast Output Enable Register logic option turned on for a node that is in QFBK mode.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.