List of Messages |
CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the nodes because the I/O cell already contains a register that has a different out_clk signal than the register to be packed. Each I/O cell can have only one distinct out_clk signal. If the two nodes have one out_clk signal, other registers in the design might also one of the above logic options turned on. If these registers were packed with the I/O cell in an earlier phase of register packing, there might be conflicting clock signals, because Analysis & Synthesis generally does not pack registers into I/O cells.
ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, make sure that the specified nodes have the same out_clk signal.
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