List of Messages |
CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified LCELL node. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the logic cell into an I/O node because the LCELL has a location constraint to a region in which the device has I/O cells. Packing the LCELL into an I/O cell would prevent the design from fitting in the device.
ACTION: Check the location assignment on the LCELL to see that the region contains an I/O cell location.
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