List of Messages |
CAUSE: You turned on the Fast Input Register logic option for the specified register. The specified node can also be a PLL compensated pin in source synchronous mode. However, the register has no valid packable connection from its input port to an I/O pin. The Fitter cannot honor the assignment because there is no I/O cell in which to pack the register. This condition can also arise if the connection between the input pin and register is global, because global connections cannot be absorbed by register packing.
ACTION: Remove the Fast Input Register logic option assignment on the register or remove any Global Signal logic option assignments between the input pin and register.
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