List of Messages |
CAUSE: You turned on the Fast Input Register logic option for the specified register. The specified node can also be a PLL compensated pin in source synchronous mode. However, the register has no valid packable connection from its input port to an I/O pin. The Fitter cannot honor the assignment because the I/O buffer associated with the I/O fans out to multiple destinations. For a register to be packed into an input I/O cell, the I/O input buffer must only drive the DATA_D port of the register, and no additional fanouts.
ACTION: Remove the Fast Input Register logic option assignment on the register or modify the design so that the I/O input buffer only drives one destination register.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.