List of Messages |
CAUSE: The specified PLL and its specified input clock are driven by a remote clock input pin. As a result, the input clock delay may not be fully compensated by the PLL.
ACTION: If you do not care about compensation of the input clock(s), use the no compensation mode instead. Otherwise, connect the input clock to a dedicated clock input pin.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.