List of Messages |
CAUSE: You specified the input clock frequency and the specified I/O standard for the specified input pin, which is an input clock of the specified fast or enhanced PLL. However, the Fitter cannot place the fast or enhanced PLL, because the input clock frequency is higher than the specified maximum input clock frequency, which the target PLL I/O pin supports for the I/O standard.
ACTION: Modify the design, so that the input clock frequency of the PLL is less than the maximum frequency or assign the specified input clock pin to a different location.
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