List of Messages
Parent topic: List of Messages

ID:16230 Your design exceeds the maximum number of single-ended 2.5-V I/O pins allowed in bank <name> with LVDS TX pin <name>. Reduce the number of single-ended 2.5-V I/O pins in the bank or design and rerun the Compiler. Refer to the Signal Integrity Design Guidelines for more information. Ensure the total percentage of SSN for the following single-ended I/O pins does not exceed 100%.

CAUSE: Your design exceeds the maximum number of 2.5-V SE I/O pins allowed in the specified I/O bank, resulting in high SSN for the LVDS TX pin.

ACTION: Reduce the number of single-ended 2.5-V I/O pins in the bank or design and rerun the Compiler.

Parent topic: List of Messages

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