| List of Messages | |
CAUSE: The specified input pin at the specified I/O pin is using the SSTL-2 I/O standard and sharing the VREF pin with DQ or DQS pins in the same I/O bank. These DQ or DQS pins are placed less than 3 pads away from the VREF pin, which may affect the voltage performance during SDRAM write operations.
ACTION: No action is required.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.