List of Messages |
CAUSE: In the current design, the Design Assistant found the specified number of nodes where you connected a clock signal source so it drives both input clock ports and ports that are not input clock ports. A clock signal source should drive only input clock ports of registers. When a design contains a clock signal source that connects to non-clock ports, the design is considered asynchronous, which can cause problems in the design. The submessage(s) of this message list the node(s) that the Design Assistant found.
ACTION: Remove the connections between the clock signal sources and any ports they drive that are not input clock ports of registers.
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