List of Messages |
CAUSE: In the current design, the Design Assistant found the specified number of nodes where combinational logic directly drives the write enable signal of asynchronous RAM. However, glitches in the combinational logic can cause the asynchronous RAM to become corrupted; therefore, combinational logic should not directly drive write enable signals of asynchronous RAM.
ACTION: Use a register between the combinational logic and the asynchronous RAM, or replace the asynchronous RAM with synchronous memory.
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