List of Messages
Parent topic: List of Messages

ID:307057 PLL clock <name> (with phase shift <name>) must be phase shifted between 72 to 108 degrees more than PLL clock <name> (with Phase shift <name>)

CAUSE: The requirement on the memory interface needed for using macro timing parameters in the ALTMEMPHY timing analysis has been violated.

ACTION: Change the design so that the PLL is phase shifted correctly.

Parent topic: List of Messages

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