| List of Messages | |
CAUSE: The requirement on the memory interface needed for using macro timing parameters in the ALTMEMPHY timing analysis has been violated.
ACTION: Change the design so that the DDR3-SDRAM pin is fed by an OUTPUT_PHASE_ALIGNMENT WYSIWYG with the correct degree phase shift.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.