List of Messages
Parent topic: List of Messages

ID:307013 PLL clock driving DDR3-SDRAM CK pins <name> must be the same clock driving the DQS pins (currently <name>)

CAUSE: The requirement on the memory interface needed for using macro timing parameters in the ALTMEMPHY timing analysis has been violated.

ACTION: Change the design so that the PLL clock driving DDR3-SDRAM CK pins is the same clock driving the DQS pins.

Parent topic: List of Messages

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