List of Messages
Parent topic: List of Messages

ID:307072 Input clock to the ALTMEMPHY PLL, <name>, when fed by another PLL, must come from the dedicated PLL to the PLL cascade path.

CAUSE: The jitter or uncertainty values used in the ALTMEMPHY timing analysis for the memory interface depend on a specific circuit topology.

ACTION: To obtain accurate jitter or uncertainty values, you must change the design so that the input clock to the ALTMEMPHY PLL, when fed by another PLL, comes from the dedicated PLL to the PLL cascade path.

Parent topic: List of Messages

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