List of Messages
Parent topic: List of Messages

ID:307070 Input clock of the PLL <name> must be fed by a dedicated input pin.

CAUSE: The jitter or uncertainty values used in the ALTMEMPHY timing analysis for the memory interface depend on a specific circuit topology.

ACTION: To obtain accurate jitter or uncertainty values, you must change the design so that the input clock of the PLL is fed by a dedicated input pin.

Parent topic: List of Messages

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