List of Messages
Parent topic: List of Messages

ID:307010 Memory clock <name> must be fed by a DDIO_OUT WYSIWYG whose clk input is inverted

CAUSE: The requirement on the memory interface needed for using macro timing parameters in the ALTMEMPHY timing analysis has been violated.

ACTION: Change the design so that the memory clock is fed by a DDIO_OUT WYSIWYG whose clk input is inverted.

Parent topic: List of Messages

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