List of Messages |
CAUSE: You specified a PLL that results in the specified phase frequency detector (PFD) frequency for the specified input clock; however, the frequency is less than the specified minimum required PFD frequency, which is the specified amount times the bandwidth value. The PFD frequency must be at least the specified amount times the bandwidth value to ensure optimal PLL performance.
ACTION: Change the PLL's multiply and/or divide ratios or increase the input frequency in order to increase the PLL's PFD frequency to at least the specified amount times the bandwidth value. If you specified internal parameters, set the CHARGE_PUMP_CURRENT, LOOP_FILTER_R, and the LOOP_FILTER_C parameters so that PFD frequency is at least the specified amount times the bandwidth value.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.