List of Messages |
CAUSE: The specified PLL has an input clock that is not driven by a dedicated input pin. As a result, jitter performance depends on the switching rate of other design elements. This can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.
ACTION: If you want better jitter performance, connect the input clock to an input pin only, or assign the input pin to a dedicated input clock location for the PLL only. If you do not want better jitter performance, no action is required.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.