List of Messages |
CAUSE: The specified output was specified as the compensated output of the PLL. However, it uses cascaded counters, which incur additional delays compared to non-cascaded counters. The additional delay is not fully compensated by the PLL when going through a cascaded counter connection.
ACTION: Change the multiply and/or the divide ratios of the output clock so that cascaded counters are not used, or change the PLL to No Compensation mode if compensation is not required.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.