CAUSE: The
ADD_PHASE_TRANSFER_REG parameter of the specified
OUTPUT_PHASE_ALIGNMENT primitive is set to an illegal value. If the
ADD_PHASE_TRANSFER_REG parameter is TRUE, then the
INVERT_PHASE parameter mus be set to FALSE and vice versa if the following conditions are met:
-
use_phase_ctrlin is set to FALSE and
-
invert_phase is not set to dynamic and
-
add_phase_transfer_reg is not set to dynamic and
-
bypass_input_register is set to FALSE and
-
use_delayed_clock is set to FALSE and
-
use_phasectrl_clock is set to TRUE and
- the datain[] input signal is not VCC or GND and
- the sources clocks phase is within +1 or -1 delay buffer.
To determine the source's clock phase, use the following conditions:
- if phase_setting is set to 0 and invert_phase is set to add_phase_transfer_reg, then phase difference = 0 (definite violation)
- if phase_setting is set to 0 and invert_phase is not add_phase_transfer_reg, then phase difference = 3 to 8 (definitely not a violation)
- if phase_setting is in the inclusive range [1, DLL_delay_chain_length/2] and invert_phase is set to add_phase_transfer_reg, then phase difference = phase_setting
- if phase_setting is in the range [DLL_delay_chain_length/2 .. 7] and invert_phase is set to add_phase_transfer_reg, then phase difference = (phase_setting - DLL_delay_chain_length)
- if invert_phase is not set to add_phase_transfer_reg, then phase difference = (phase_setting - DLL_delay_chain_length/2)
ACTION: Check the design and make sure that the specified parameter values are not in conflict with each other.