List of Messages |
CAUSE: ATX phase-locked loop (PLL) on production silicon has frequency limitations based on placement.
ACTION: Refer to Stratix V Errata Sheet to ensure that the data rate for the specified ATX PLL is within the documented performance specification for the placement. Otherwise, manually assign this ATX PLL to the appropriate location based on the Stratix V Errata Sheet."
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.