List of Messages |
CAUSE: You assigned the PLL input clock pin. However, this logic option assignment is illegal for PLL input clock pins. When this condition occurs, Analysis & Synthesis ignores the Virtual Pin assignment for the pin.
ACTION: No action is required. However, to avoid receiving this message in the future, remove the Virtual Pin assignment from the pin.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.