List of Messages |
CAUSE: The locked clock port on the PLL should be connected when the feedback output port is connected. Although it is unnecessary to connect the locked clock, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready.
ACTION: Update the design by connecting the locked port of the PLL.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.