List of Messages |
CAUSE: The size of the memory you specified in a design file (Block Design File (.bdf), Text Design File (.tdf), VHDL Design File(.vhd), Verilog Design File (.v), or EDIF Input File (.edf)) does not match the size of the memory you specified in the MEM_INIT parameter. This condition occurs when you specify a memory size in the design file that is greater than the memory size defined in the MEM_INIT parameter. The Quartus Prime software is therefore setting the initial value for the remaining addresses to 0.
ACTION: If you do not want the initial value for the remaining addresses set to 0, make sure that the design file and the MEM_INIT parameter contain the same memory depth values for the memory block.
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