List of Messages |
Active-Low Clear: | Active-Low Preset: | Active-High Aload: | Active-High Clock Enable: | Active-High Clock: | Power-up State: | D_in: | Register Reduces To: |
GND | GND | ||||||
VCC | GND | VCC | |||||
GND | !Clear | ||||||
VCC | VCC | VCC | Adata | ||||
VCC | VCC | GND | GND | Power-up state | |||
VCC | VCC | GND | VCC or GND | Power-up state | |||
VCC | GND | VCC or GND | Low | GND | |||
VCC | GND | VCC or GND | High | VCC | |||
VCC | GND | GND | Low | GND | |||
VCC | GND | GND | High | VCC | |||
VCC | GND | Low | GND | GND | |||
VCC | GND | High | VCC | VCC |
ACTION: If you intended the register to behave in this manner, no action is required. Otherwise, check the design file for errors and make sure the project's logic does not reduce to any of these combinations. If you want to specify a particular power-up level on a register, you can use the Power-Up Level option. If you want to specify that the Analysis & Synthesis should not use a nondefault setting for unspecified power-up levels in order to minimize delays or design resources, set the ALLOW_POWER_UP_DONT_CARE option to OFF in the Quartus Prime Settings File (.qsf).
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