List of Messages |
CAUSE: The clock for the specified register is stuck at VCC or GND, or its clock enable is stuck at GND, so Analysis & Synthesis reduced the register to its power-up state. You may have specified this condition in the design file, or the condition may be the result of logic synthesis.
ACTION: If you expected this result, no action is required. Otherwise, check the design file for errors. Or, you can add a preset and/or clear input to toggle the register.
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