List of Messages |
CAUSE: You can use only phase-locked loop (PLL) counters 0-3 or 14-17 to drive the PHY clock tree in Stratix V devices. The Fitter was unable to use one of these two sets to drive the PHY clock tree in your current design.
ACTION: Use the set_location_assignment <PLL counter location> -to <PLL output signal> assignment to constrain the PLL counters that drive the PHY clock tree.
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