List of Messages |
CAUSE: The Phase-Locked Loop (PLL) feedback signal could not be routed to compensate for the targeted clock network type as determined automatically by the fitter or a MATCH_PLL_COMPENSATION_CLOCK setting. This may affect timing closure in certain cases.
ACTION: The feedback path type can be manually specified as a hard constraint with the PLL_FEEDBACK_CLOCK_SIGNAL assignment. Possible values for the feedback path type are: Global Clock, Regional Clock, Far Global Clock, Far Regional Clock, Near Global Clock, and Near Regional Clock.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.