List of Messages
Parent topic: List of Messages

ID:14551 Multiple Partial Reconfiguration LogicLock regions occupy the <name> region originating at (<number>, <number>). The combination of these regions may only use <number> global signals.

CAUSE: Your floorplan has more than one partial reconfiguration LogicLock region in a row clock region.

ACTION: Modify the floorplan such that only one Partial Reconfiguration region occupies the row clock region indicated. Alternatively, ensure that the indicated number of global signals is not violated.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.