List of Messages |
CAUSE: The following PLLs are set to be compensated with a clock network, but its compensated clocks are feeding both the global and regional clock networks. The PLL will compensate for output clocks.
ACTION: Use the Global Signal option assignments to set a common clock network type for the compensated clock signals, or use the Match PLL Compensation option assignment to choose a PLL output clock to compensate.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.