List of Messages |
module test1 (input oe1, data1, in, output out, inout bidir); wire tribuf, tmp; assign tribuf = oe1 ? data1 : 1'bz; and(tmp, in, tribuf); assign bidir = tribuf; assign out = tmp; endmoduleIn the following design, the node triwire is converted to a selector.
module test2 (input oe1, data1, oe2, data2, in, output out); wire triwire, tmp; assign triwire = oe1 ? data1 : 1'bz; assign triwire = oe2 ? data2 : 1'bz; and(tmp, in, triwire); assign out = tmp; endmoduleSee the sub-messages below to view a list of the affected tri-state nodes and a more detailed Help.
ACTION: Avoid this warning by either removing the non-tri-state fan-outs of the affected tri-state nodes or replacing the tri-state nodes with non-tri-state logic.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.