| List of Messages | |
CAUSE: The specified net is connected to a signal or variable declared in a VHDL or System Verilog package, but does not have a source. The net will be connected to GND.
ACTION: If you don't care about the value of the net, no action is required. If you want to avoid receiving this message in the future or if you care about the value of the net, connect the net to a constant that represents its default value using a signal or variable assignment statement.
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