List of Messages |
CAUSE: In the Test Bench name box in the New Test Benches dialog box, you did not specify a Verilog HDL test bench file name or a VHDL test bench file name. You cannot continue unless you specify a test bench file name, or turn on None in the NativeLink Settings dialog box.
ACTION: Click OK to close the message dialog box, and then specify a legal test bench file name.
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