List of Messages |
CAUSE: You attempted to overwrite the target Verilog Design File (.v). However, the Quartus Prime software could not remove the existing VHDL or Verilog HDL Design File. This message can occur when the target design file is read-only or when you do not have permission to edit the design file.
ACTION: Click OK to close the message dialog box, and then make sure the file is not read-only and that you have permission to edit the file and then create the new VHDL or Verilog Design File again.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.