List of Messages |
CAUSE: You attempted to update the specified Text Design File (.tdf) for the selected block. However, the design file was not created by the Quartus Prime software, and the Quartus Prime software will place the code generated to update the file at the end of the Verilog Design File, VHDL Design File, or TDF.
ACTION: No action is required. You may need to manually edit the design file to incorporate the additional code at the end of the file.
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