List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you created the specified finite state machine with a reset state that is too complex (for example, you specified the use of an asynchronous reset followed by an asynchronous load). As a result, the Quartus Prime software cannot recognize the finite state machine, but instead treats the related code as regular logic.
ACTION: If you want the Quartus Prime software to recognize the finite state machine, simplify the reset state. Otherwise, no action is required.
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